1. Field of the Invention
The invention relates to a method for fabricating a plurality of semiconductor chips which emit electromagnetic radiation, having an epitaxially produced semiconductor layer stack based on nitride semiconductor material, which includes an n-conducting semiconductor layer, a p-conducting semiconductor layer and an electromagnetic radiation generating region which is arranged between these two semiconductor layers, a base on which the semiconductor layer stack is arranged, and a mirror layer, which is arranged between the semiconductor layer stack and the base.
2. Description of the Related Art
The term semiconductor layer stack based on nitride III-V compound semiconductor material is intended to encompass all semiconductor layer stacks whose main properties are determined by a nitride III-V compound semiconductor material. Nitride III-V compound semiconductor materials are all semiconductor materials which have nitrogen at the V lattice site, in particular GaN, InGaN, AlGaN and InGaAln. The semiconductor layer stack may, for example, have a conventional pn junction, a double heterostructure, a single quantum well structure (SQW structure) or a multiple quantum well structure (MQW structure). Structures of this type are known to the person skilled in the art and are therefore not explained in more detail at this point.
Semiconductor chips of the type described above convert electrical energy into electromagnetic radiation or vice versa. To do this, they usually have a semiconductor diode structure, which generates electromagnetic radiation in what is known as an active area between a p-conducting semiconductor layer and an n-conducting semiconductor layer. One problem of chips of this type is the outcoupling of the maximum possible proportion of the radiation which is generated in the electromagnetic radiation generating region.
In the case of what is known as a thin-film LED chip (LED=light emitting diode), which generally comprises a radiation-generating semiconductor layer stack arranged on a base, the thin semiconductor layers are grown epitaxially on a growth substrate wafer, which is detached after the semiconductor layers have, for example, been rebounded onto a base.
A semiconductor chip of this type is known, for example, from DE 100 20 464 A1. In this case, a reflector is formed on a surface of a semiconductor layer stack which is located on the side of the semiconductor layer stack opposite to the surface from which light emerges out of the semiconductor layer stack. The reflector is formed by a dielectric mirror or by a reflective metallic contact surface, which at the same time is also used for establishing the electrical contact of the semiconductor body. To improve the outcoupling of light, the entire free surface of the semiconductor body is roughened in order to prevent total reflection at the outcoupling surface between the semiconductor body and the environment and to thereby increase the light yield of the semiconductor chip.
A drawback of this type of semiconductor chip is that the roughening of the outcoupling surface requires at least one additional method step, entailing additional time expenditure and therefore additional costs. Furthermore, the light yield of these semiconductor chips is still well short of the theoretical maximum.
Hitherto, the prior art has not disclosed any measures for improving the light yield of semiconductor chips of the type described above which are directed at the p-conducting semiconductor layer. A particular problem of p-conducting nitride III-V compound semiconductor layers is their sensitivity to chemical or mechanical treatment. Contacts with low contact resistances can only be produced with difficulty on surfaces which have been treated in this way. Therefore, surface patterning of the p-conducting semiconductor layer by etching or mechanical roughening is not advantageous.
Therefore, as an alternative the n-conducting semiconductor layer is generally textured by means of RIE (reactive ion etching). However, this method requires the n-conducting semiconductor layer to be detached from the growth substrate wafer. The side from which the growth substrate wafer has been removed must also first of all be planarized, so that the mask layers which are required for patterning can be applied. Further process steps are required in order to pattern the surface in a suitable etching installation and then to remove the mask layer.